Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints
نویسندگان
چکیده
We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information from the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults.
منابع مشابه
On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits
This paper describes a method of identifying a set of crosstalk-induced delay faults which may need to be tested in synchronous sequential circuits. In this process, the false crosstalk-induced delay faults that need not (and/or can not) be tested in synchronous sequential circuits are also identify. Our method classifies the pairs of aggressor and victim lines, using topological information an...
متن کاملATPG for Faults Analysis in VLSI Circuits Using Immune Genetic Algorithm
As design trends move toward nanometer technology, new Automatic Test Pattern Generation (ATPG)problems are merging. During design validation, the effect of crosstalk on reliability and performance cannot be ignored. So new ATPG Techniques has to be developed for testing crosstalk faults which affect the timing behaviour of circuits. In this paper, we present a Genetic Algorithm (GA) based test...
متن کاملCompaction of Test Set for Crosstalk Induced Glitch Faults using Pattern Sequencing
Detection of crosstalk induced glitch faults is important as they can result in erroneous output if the glitch effect propagates to a primary output or to an intermediate flipflop. A new method is thus presented in this paper to generate test patterns for crosstalk induced glitch faults followed by compaction of the test set. By considering the spatial and temporal aspects between the victim an...
متن کاملOptimization of Delay and Energy in On-Chip Buses using Bus Encoding Technique
In very deep sub-micron (VDSM) fault-tolerant busses, crosstalk noise and logic faults caused due to shrinking wiresize and reduced inter-wire spacing are major factors affecting the performance of onchip interconnects, such as high power consumption and increased delay. In this paper we propose a bus optimization technique which reduce the energy and power-delay using Hamming Single Error Corr...
متن کاملSimulation Based Test Generation for Crosstalk Delay Faults in Asynchronous Sequential Circuits
A number of efforts have been recently devoted to fault modeling, fault simulation and test generation for asynchronous circuits (Shi and Makris 2004). Simulation based approach for testing gate delay faults in asynchronous sequential circuits was proposed by Sur-Kolay et al (2000). Shi and Makris (2006) have proposed a test method for path delay faults based on a design for test strategy. In s...
متن کامل